The present invention relates to a multi-layered metal line of a semiconductor device and a method for forming the same, and more particularly to a multi-layered metal line of a semiconductor device which prevents diffusion between upper and lower metal lines brought into contact with each other and a method for forming the same.
Memory cells in a semiconductor memory device operating in a high speed are formed in a stacked structure. Further, the metal line for carrying the electric signals to the respective cells is formed in a multi-layered structure. The multi-layered metal line offers advantageous design flexibility and allows the wiring resistance and current capacity to be set to an acceptable margin.
Al has been a material of choice for a metal line due to its excellent electric conductivity and its relatively easy-to-process characteristics. However, problems appear when Al is applied to form a metal line in a highly integrated semiconductor device due to undesirably increased resistance of the metal line formed with Al. In dealing with this problem caused by the increased wiring resistance due to the high integration of a semiconductor device, Cu instead of Al is currently being adopted as the suitable material for a metal line, as Cu offers relatively lower resistance than Al.
However, using Cu for all multi-layered metal lines is not considered preferable in consideration of the device characteristics and reasonable manufacturing cost. Therefore, recently, a method for forming a multi-layered metal line has been suggested, in which a lower metal line and an upper metal line are formed using Al and Cu, respectively.
Hereafter, a conventional method for forming a multi-layered metal line of a semiconductor device, in which a lower metal line and an upper metal line are respectively formed using Al and Cu, will be described with reference to FIG. 1.
A passivation layer 130 is formed on a semiconductor substrate 100 having a lower Al line 110 and an interlayer dielectric 120 formed thereon, to prevent the lower Al line 110 from being damaged in a subsequent process. A first insulation layer 140 and an etch barrier 150 for preventing the first insulation layer 140 from being etched in a subsequent process for etching a second insulation layer are sequentially formed on the passivation layer 130. A second insulation layer 160 is then formed on the etch barrier 150.
A via hole 171 is defined to expose the lower Al line 110 by etching the second insulation layer 160, the etch barrier 150, the first insulation layer 140, and the passivation layer 130. By additionally etching the second insulation layer 160 over the via hole 171 using the etch barrier 150 as an etch stop layer until the etch barrier 150 is exposed, a trench 172 is formed to delimit (or define) a metal line forming region. In this way, a dual type damascene pattern 170 composed of the via hole 171 and the trench 172 is formed.
A diffusion barrier 180 is formed on the surface of the damascene pattern 170. The diffusion barrier 180 is made of a stack of a Ti layer 181 and a TiN layer 182. A Cu layer is deposited in the damascene pattern 170, which is formed with the diffusion barrier 180. Through this, a via contact 190 for connecting the lower Al line 110 and an upper Cu line is formed in the via hole 171 of the damascene pattern 170, and the upper Cu line 191 is formed in the trench 172 of the damascene pattern 170.
As described above, when forming the multi-layered metal line according to the conventional method of forming the lower metal line of Al and the upper metal line of Cu, the diffusion barrier 180 is necessarily formed between the lower Al line 110 and the upper Cu line 190, 191 in order to prevent diffusion between the lower Al line 110 and the upper Cu line 190, 191.
In general, the stack of the Ti layer 181 and the TiN layer 182 is mainly used as a diffusion barrier in a multi-layered metal line, in which a lower metal line 110 and an upper metal line 190, 191 are formed using Al and Cu respectively.
However, the stack of the Ti layer 181 and the TiN layer 182 of the diffusion barrier 180 does not provide the sufficient thickness to effectively suppress the diffusion between the lower Al line 110 and the upper Cu line which 190, 191 that are brought into contact with each other.
Increasing the thickness of the diffusion barrier 180 formed by the Ti layer 181 and the TiN layer 182 could suppress the diffusion between the lower Al line 110 and the upper Cu line 190, 191 brought into contact with each other. Nevertheless, the increased thickness of the Ti layer 181 and the TiN layer 182 reduces the overall area of the damascene pattern 170 in which the Cu layer 190, 191 is to be filled, and this in turn causes the resistance to increase due to the reduction of the area of the metal line.
Also, when the thickness of the Ti layer 181 and the TiN layer 182 increases, it is difficult to fill the Cu layer in the via hole 171 of the damascene pattern 170 by which a void can be created in the via hole 171, and the presence of voids causes a significant increase in resistance.
Accordingly, it is not practical to adopt the way of increasing the thickness of the diffusion barrier layer 180 (having the Ti layer 181 and the TiN layer 182) to suppress the diffusion between the lower Al line 110 and the upper Cu line 190, 191 brought into contact with each other.